1. Field of the Invention
The present invention relates to a liquid crystal display, and more particular to a gate driver on array (GOA) circuit and a liquid crystal display device.
2. Description of Related Art
In an active matrix liquid crystal display device, each pixel has a thin film transistor (TFT), the gate of the TFT is connected to a horizontal scanning line, the drain of the TFT is connected to a vertical data line, and the source of the TFT is connected to a pixel electrode. Applying sufficient voltage on the horizontal scanning line, every TFT on the horizontal scanning line will be turned on. The horizontal scanning lines are connected to the vertical data line in order to write a display signal voltage on the data line to the pixel, and achieve the effect of controlling the color through controlling different transmittance of the liquid crystals.
Currently, the driving of the horizontal scanning lines of an active matrix liquid crystal display (LCD) panel is using an external IC connected at the outside of the panel. The external IC can control every stage of the horizontal scanning lines to charge and discharge.
The gate driver on array (GOA) technology can utilize the original fabrication process of the LCD panel to fabricate a driving circuit of the horizontal scan lines on the substrate around the display region such that the driving circuit can replace the external IC to drive the horizontal scan lines. The GOA technology can reduce the bonding process for the external IC to increase productivity and reduce product cost such that the LCD panel is more suitable for the narrow frame or no frame display product.
The conventional GOA circuit generally includes multiple cascaded GOA units; each of the GOA units corresponds to drive a stage of horizontal scanning line. The GOA unit mainly includes a pull-up circuit, a pull-up control circuit, a transfer circuit, a pull-down circuit, a pull-down holding circuit, and a boast capacitor used to boost a voltage. Wherein the pull-up circuit is mainly responsible for outputting a clock signal as a gate signal; the pull-up control circuit is responsible for controlling a turn-on time of the pull-up circuit, and generally connected to a transfer signal or a gate signal from the previous stage GOA unit; the pull-down circuit is responsible for pulling down the gate signal to a low level voltage immediately, that is, turning off the gate signal; the pull-down holding circuit is responsible for holding a gate output signal or the gate signal of the pull-up circuit (commonly referred to as a Q node) at a turn-off state (i.e., a negative voltage). Usually, two pull-down holding circuits function alternatively; the boast capacitor is responsible for secondarily boosting the voltage of the Q node to facilitate the G (N) output of the pull-up circuit.
As shown in FIG. 1, a schematic diagram of a conventional GOA circuit is shown. In FIG. 1, a GOA unit comprises: a pull-up control circuit 100, a pull-up circuit 200, a transfer circuit 300, a pull-down circuit 400, a boast capacitor 600, a first pull-down holding circuit 510, and a second pull-down holding circuit 520.
FIG. 2 shows waveforms of input signals, output signals, and key nodes of the GOA circuit in FIG. 1. Wherein, CK and XCK are two complementary signals in phase; VSS2<VSS1; G (N) and G (N+1) are gate output signals of Nth stage and (N+1) th stage. As shown in FIG. 2, G(N) will be pulled down to a low level voltage VSS1, and P (N) will be pulled down to a low level voltage VSS2 which is lower than VSS1 when Q (N) and G (N) are at high level voltages.
However, the conventional GOA circuit has following shortcomings:
First, the voltage of the node Q (N) is not boosted enough in a first time stage, which will affect the voltage level of the node Q (N) in a second time stage. The voltage lack of the node Q (N) will directly affect the output of G (N), the transfer of the circuit, and the starting speed of the pull-down circuit. Specifically, because the voltage lack of the node Q (N), the starting speed of T21 and T22 will be delayed, and the output of G (N) and ST (N) exist a larger delay.
Besides, the delay of G (N) will affect the charging of the pixel TFT in the display area. In a serious case, a charging error will generate such that the screen is abnormal.
In addition, the delay of ST (N) will directly affect the starting of the pull-down holding circuit. When the delay of ST (N) is too serious, the voltage boost of the node P (N) will be slow such that the voltage of the node P (N) in the non-operation period is delayed. In the serious case, the ripple current will generate at Q (N) and G (N) in order to affect the operation of the circuit.
Furthermore, the pulling down of ST (N) will have a risk when the pulling down is executed by the XCK signal. Specifically in the pulling down circuit, except the pulling down of P (N), no more pulling down preventing design is existed. If the pulling down by a single side is failed, the entire circuit is failed. When the ST (N) signal is used more as in FIG. 1, how to handle the ST (N) signal is especially important. If the ST (N) signal is not handled properly, the entire pull-down holding circuit will fail, and the entire GOA circuit will also fail in a serious case.